The development of integrated circuits (ICs) has become increasingly complex, due in large part to the ever increasing functionality offered by newly developed circuitry. Integrated circuits continue to surpass milestones in development, as more and more functionality is packaged into smaller sizes. This enhanced functionality and the greater number of transistors packaged in an integrated circuit requires more rigorous testing requirements to insure reliability once the device is commercialized. Thus, new integrated circuit designs are repeatedly tested and debugged during the development process to minimize the number and severity of errors that may subsequently arise. Regardless of the rigor of the developmental testing, invariably a certain percentage of manufactured devices will fail prematurely.
Thus, a problem existing in the semiconductor industry is in the testing of manufactured chips. Even assuming a good, error-free logic design, it is well known that various faults and errors can enter into the production process, which can result in functional defects in a manufactured chip. These faults can enter through a variety of causes in the numerous manufacturing process steps and can affect any of the different gates, switches or lines on the chip. To prevent such devices from being sold or used in systems, typically some level of testing is performed on manufactured chips to identify those that may fail prematurely.
A number of different types of testing have been used to minimize the possibility of premature failure of manufactured chips. One of the more popular types of testing is scan testing. Scan testing is a well recognized design-for-test (“DFT”) technique used for addressing certain testing problems in very large scale integrated (“VLSI”) circuits. A full scan design technique transforms a given sequential circuit into a combinational circuit and shift register (referred to as a scan register) for the purpose of testing. This transformation makes it possible to obtain almost complete fault coverage using an Automatic Test Pattern Generation (“ATPG”) program. Typically, as part of the scan test, large circuits are partitioned into smaller combinational circuits to facilitate fault isolation and failure analysis.
The scan design technique implements all or most of the state elements in the device under test, such as flip-flops and latches, as scannable flip-flops, which often are referred to as scan-flops. An ATPG program can treat the state elements as pseudo inputs and outputs of the device. During typical testing, a scan-path is first tested by shifting a simple sequence of 1s and 0s through chained scan-flops. The ATPG program then generates test vectors that are applied to test the combinational logic. The device then returns to normal operational mode, typically for one clock cycle, to capture the response of the combinational circuit in the scan-flops. The captured response is unloaded via the scan-path and, at the same time, the state element values corresponding to the next test vector are loaded. This testing sequence repeats until all test vectors are applied.
Tools exist to help evaluate resulting data from the scan test and identify path(s)/logic gate(s) exhibiting stuck-at faults. While such analysis tools can provide a level of assistance in isolating faults, they also create a level of vulnerability, since use of such tools allows for reverse engineering of the integrated circuit design.
A need exists, therefore, for design obfuscation for an IC, including during scan testing. The present invention addresses such a need.